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pt6355 vfd driver/controller ic tel: 886-66296288 ? fax: 886-29174598 ? http://www.princeton.com.tw ? 2f, 233-1, baociao road, sindian, taipei 23145, taiwan description pt6355 is a vacuum fluorescent display controller driven 5/16, 6/16, 14/16 and 15/ 16 duty factors. eight to eighteen segment output lines, seven to ten grid output lines, ten segment/grid output drive lines, 8-bit x 6-channel a-d converter, built-in noise filter are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro-computer. pt6355 also provides 4 serial interfaces via the cs, sin, sout, sclk pins. housed in 44-pin, lqfp package, pt6355?s pin assignment and application circuit are optimized for easy pcb layout and cost saving benefits. application ? micro-computer peripheral device features ? cmos technology ? internal pull-low resistor ? 4-step dimming circuitry ? 8 to 18 segment outputs ? 7 to 10 grid outputs ? built-in noise filter in se rial clock and serial input pins with 2 mhz sampling ? 8-bit x 6 channels analog-to-digital converter with +3lsb accuracy ? available in 44-pin, lqfp package block diagram
pt6355 v1.6 2 application circuit
pt6355 v1.6 3 order information valid part number package type top code PT6355-LQ/pt6355 44-pin, lqfp PT6355-LQ/pt6355 pin configuration
pt6355 v1.6 4 pin description pin name i/o description pin no. vcc - power supply 1, 44 osc2 o oscillation output pin 2 vss - power supply 3 osc1 i oscillation input pin 4 /reset i reset input pin active ?l? internal pull-high resistors are connected between this pin and the vcc pins. 5 an5 to an0 i analog to digital pin 6 to 11 /cs i chip select 12 sin i serial input pin the clock is read twice with a 2mhz sampling rate in order to judge if the signal is a noise or not. 13 sout o n-channel open drain serial output pin during the reset condition, this pin is in high-impedance state. 14 sclk i serial clock input pin the clock is read twice with a 2mhz sampling rate in order to judge if the signal is a noise or not. 15 vee - pull-down power supply supplies voltage to pull-down resistors 16, 17 gr0/p0 to gr7/p7 o p-channel open drain grid/port output pins this pin acts as either a grid output pin or as an ordinary port terminal. during the reset condition, this pin is set to vee via a pull-down resistor. 18 to 25 gr8/seg17 to gr17/seg8 o p-channel open drain grid/segment output pins this pin acts as either a grid output pin or as an segment output pin. during the reset condition, this pin is set to vee via a pull-down resistor. 26 to 35 seg0 to seg7 o p-channel open drain segment output pin during the reset condition, this pin is set to vee via a pull-down resistor. 43 to 36
pt6355 v1.6 5 port block diagram ? grid/port pin & grid/segment pin ? grid pin ? segment pin ? sout pin ? /cs pin ? sin, sclk pins ? a-d input ? osc1 & osc2 pins notes: 1. * = dimmer signal is for setting the t off time 2. ** = high-break down voltage p channel transistor
pt6355 v1.6 6 function description commands command 0: display data setting b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 - number of segment setting: 00: 16 or less 01: 17 or above number of grid setting: 00: 7 01: 8 10: 9 11: 10 command 1: display state setting b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 - - on/off setting: 1: display is turned on 0: display is turned off display duty setting: 11: 15/16 10: 14/16 01: 6/16 00: 5/16
pt6355 v1.6 7 command 2: grid selection b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 - grid start pin settings: 0000: d17 0001: d16 0010: d15 0011: d14 0100: d13 0101: d12 0110: d11 0111: d10 1000: d9 1001: d8 1010: d7 command 3: port data settings b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 p3 to p0 / p7 to p4 output data port selection settings: 0: p3 to p0 1: p7 to p4 note: in the event that a port has been selected (example: b4 = 0, p3 to p0 is selected), and at the same time the grid output pin function is enabled, then the grid output having a higher priori ty than the port function will override the port selection.
pt6355 v1.6 8 serial interface portocol byte portocol note: when the cs signal is ?high? , sout is in high-impedance state. command 0 potocol notes: 1. the serial data which is transmitted after the execution of command 0 is recogni zed as a display data. a-d data 6 and above are defined as ?x?. 2. after transferring a display data, the cs must be set to ?high? level. commans 1 to command 3
pt6355 v1.6 9 serial communication format 3-byte transfer: 17 segments and above note: the 2 bytes namely ?x? data is outputted before t he a-d valid data. please refer to the diagram above. 2-byte transfer: 16 segments or below note: the 2 bytes namely ?x? data is outputted before t he a-d valid data. please refer to the diagram above. 2-byte transfer: 8 segments or less note: the 2 bytes namely ?x? data is outputted before t he a-d valid data. please refer to the diagram above.
pt6355 v1.6 10 display timing
pt6355 v1.6 11 segment/grid setting example port gr seg grid: 7 segment: 8 grid: 10 segment: 8 grid: 10 segment: 16 grid: 7 segment: 18 1 seg0 s1 s1 s1 s1 2 seg1 s2 s2 s2 s2 3 seg2 s3 s3 s3 s3 4 seg3 s4 s4 s4 s4 5 seg4 s5 s5 s5 s5 6 seg5 s6 s6 s6 s6 7 seg6 s7 s7 s7 s7 8 seg7 s8 s8 s8 s8 9 gr17 seg8 g7 g10 s9 s9 10 gr16 seg9 g6 g9 s10 s10 11 gr15 seg10 g5 g8 s11 s11 12 gr14 seg11 g4 g7 s12 s12 13 gr13 seg12 g3 g6 s13 s13 14 gr12 seg13 g2 g5 s14 s14 15 gr11 seg14 g1 g4 s15 s15 16 gr10 seg15 g3 s16 s16 17 gr9 seg16 g2 g10 s17 18 gr8 seg17 g1 g9 s18 19 p7 gr7 g8 g7 20 p6 gr6 g7 g6 21 p5 gr5 g6 g5 22 p4 gr4 g5 g4 23 p3 gr3 g4 g3 24 p2 gr2 g3 g2 25 p1 gr1 g2 g1 26 p0 gr0 g1
pt6355 v1.6 12 bit allocation for display memory address b7 b6 b5 b4 b3 b2 b1 b0 grid 09 16 seg17 seg16 0a 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 0b 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 0 0d 16 seg17 seg16 0e 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 0f 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 1 11 16 seg17 seg16 12 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 13 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 2 15 16 seg17 seg16 16 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 17 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 3 19 16 seg17 seg16 1a 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 1b 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 4 1d 16 seg17 seg16 1e 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 1f 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 5 21 16 seg17 seg16 22 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 23 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 6 25 16 seg17 seg16 26 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 27 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 7 29 16 seg17 seg16 2a 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 2b 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 8 2d 16 seg17 seg16 2e 16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 2f 16 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 grid 9
pt6355 v1.6 13 reset function to enable the reset function of pt6355, the /reset pin must be set at ?l? level for 2 s or more. after which the /reset pin reverts back to ?h? level and then the reset is re leased. the /reset pin returned to an ?h? level when the osc1 oscillation is stable and the voltage of the power source is between 4.0 v and 5.5 v. it is very important to note that the reset input voltage is less than 0.2v cc when the v cc is 4 v. the figure below is an example of a reset circuit. oscillation circuit an oscillation circuit is construct ed by connecting a capacitor between o scillation pins -- osc1 and osc2 and v ss . the oscillation pins -- osc1 and osc2 must be as ?short? as possible. if you are supplying a clock externally, apply the clock signal to osc1 and make osc2 pin floati ng or open. please refer to the diagram below. setting unused pins if a segment or grid pin will not be used, just leave it floating or open. the a nalog input pin, howev er, must be connected to v cc or v ss via a resistor if it is not used. please refer to the table below. pin type connection segment open grid open analog input connect to v cc or v ss via a resistor
pt6355 v1.6 14 absolute maximums ratings parameter symbol conditions ratings unit power source voltage v cc -0.3 to 7.0 v pull-down power source voltage vee v ss -38 to v cc +0.3 v input voltage (an0~an5) vi -0.3 to v cc +0.3 v input voltage (/cs, sin, sclk) vi -0.3 to v cc +0.3 v input voltage (/reset) vi all voltages are based on v ss output transistors are cut off. -0.3 to v cc +0.3 v output voltage (gr0~gr17) (seg0~seg17) vo all voltages are based on v ss . output transistors are cut off. a waveform with frequency of 450 s or more and a pulse width of 30 s or less. connect only capacitor load (cl = 200 pf) v cc -38 to v cc +0.3 v output voltage (sout) vo all voltage are based on vss. output transistors are cut off. -0.3 to v cc +0.3 v power dissipation pd ta=25 600 mw operating temperature topr - -40 to +85 storage temperature tstg - -65 to +150 recommended operating conditions (unless otherwise specified, v cc = 5 v, ta = -20 to +85 ) parameter symbol min. typ. max. unit power source voltage v cc 4.5 5.0 5.5 v power source voltage v ss 0 v pull-down power source voltage vee v cc -35 v cc v ?h? input voltage (/cs, sin, sclk) vih 0.75v cc v cc v ?h? input voltage (/reset) vih 0.8v cc v cc v ?l? input voltage (/cs, si n, sclk) vil 0 0.25v cc v ?l? input voltage (/reset) vil 0 0.2v cc v recommended operating conditions (unless otherwise specified, v cc = 5 v, ta = -20 to +85 ) parameter symbol min. typ. max. unit ?h? total peak output current note1 gr0~gr17, seg0~seg17 ioh (peak) -240 ma ?h? total peak output current gr0~gr17, seg0~seg17 ioh (avg.) -120 ma ?h? peak output current note2 gr0~gr17 ioh (peak) -40 ma ?h? peak output current note2 seg0~seg7 ioh (peak) -20 ma ?l? peak output current sout note2 iol (peak) 10 ma ?h? peak output current note3 gr0~gr17 ioh (avg.) -18 ma ?h? peak output current note3 seg0~seg17 ioh (avg.) -7 ma ?l? peak output current note3 sout iol (avg.) 5.0 ma main clock input oscillator note4 frequency f (osc1) 4.0 5.2 mhz serial i/o external clock frequency f (sclk)) 250 khz notes: 1. the total output current is the sum of all the current flowing through all the applicable ports. the total average current is the average/ or mean value measured over 100 ms. the total peak current is the peak value of all the currents. 2. the peak output current is the peak current flowing in each port. 3. the average output current is an av erage or mean value measured per 100 ms. 4. under the condition that the o scillation frequency has a 50% duty cycle.
pt6355 v1.6 15 electrical characteristics (unless otherwise specified, v cc = 5 v, ta = -20 to +85 ) parameter symbol conditions min. typ. max. unit gr output ioh = -18 ma v cc -2 v ?h? output voltage seg output voh ioh = -7 ma v cc -2 v ?l? output voltage sout vol iol = 5 ma 2.0 v sin,sclk,/cs 0.5 v hysteresis /reset,osc1 vt+~vt- v cc = 5v 0.5 v sin,sclk,/cs 5.0 a /reset 5.0 a ?h? input current osc1 vih vi = v cc 4.0 a sin,sclk,/cs -5.0 a /reset -150 a ?l? input current osc1 note vil vi = v ss -0.8 ma output load current gr0~gr17 seg0~seg17 iload vee = v cc -35 v, vol = v cc , output transistors off 250 500 750 a output leakage current gr0~gr17 seg0~seg17 ileak vee = v cc -35 v, vol = v cc -35 v, output transistors off -10 a ram hold voltage vram when the clock is stopped 2.0 5.5 v power source current icc v cc = 5 v, f(osc1) = 4 mhz, output transistors off when a-d converter is operating 0.5 1.0 ma note: see osc1 & osc2 pins port diagram a-d converter characteristics (unless otherwise specified, v cc = 5 v, ta = -20 to +85 ) parameter symbol conditions min. typ. max. unit resolution 8 bits absolute accuracy (excluding quantization error) v cc = 5.12 v +3 lsb conversion time tconv 100 tc (osc1) analog input voltage via 0 v cc v analog port input current iia 0.5 5.0 a ladder resistor rladder 35 k ?
pt6355 v1.6 16 timing requirments (unless otherwise specified, v cc = 5 v, ta = -20 to +85 ) parameter symbol min. typ. max. unit reset input ?l? pulse width tw (/reset) 2 s main clock input cycle time (osc1 input) tc (osc1) 192 ns main clock input ?h? pulse width (osc1 input) twh (osc1) 60 ns main clock input ?l? pulse width (osc1 input) twl (osc1) 60 ns serial clock input cycle time note2 tc (sclk) 5 clks serial clock input ?h? pulse width note2 twh (sclk) 2 clks serial clock input ?l? pulse width note2 twl (sclk) 3 clks serial input set-up time note2 tsu (sin-sclk) 2 clks serial input hold time note2 th (sclk-sin) 3 clks serial input set-up time tsu (/cs) 50tc (osc1) ns serial input hold time th (/cs) 50tc (osc1) ns serial clock interval time trec (sclk) 50tc (osc1) ns notes: 1. tc (osc1) = 1/fosc 2. the unit means the number of noise filter sampling clock [2 x tc (osc1)] 3. test mode frequency measurement (refer to diagram): a. fosc= 2 x frequency value outputted by the cs pin. b. twh (sclk) = [(1/fosc) x 2] x 2 c. twl (sclk) = [(1/fosc) x 2 ] x 3 d. trec (sclk) = [50 x (1/fosc)] e. twh (sclk), twl (sclk) & trec (sclk) are very important factors in writing the pt6355 software program.
pt6355 v1.6 17 switching characteristics (unless otherwise specified, vcc = 5 v, ta = -20 to +85 ) parameter symbol conditions min. typ. max. unit serial i/o output delay time note2 td (sclk-sout) 4 clks serial i/o output valid time note2 tv (sclk-sout) 4 clks high break down voltage p-channel open drain output rising time tr (pch) cl = 100 pf vee = v cc -35 v 1.8 s external capacitor size note3 cosc 22 pf notes: 1. tc(osc1) = 1/fosc 2. the unit means the number of noise filter sampling clock (2 x tc(osc1)). 3. an external capacitor size varies with a mounted condition. output switching characteristics measurement application circuit timing diagram
pt6355 v1.6 18 package information 44-pin, lqfp (body size: 10 x 10 mm, pitch size: 0.8 mm, thk body: 1.40 mm)
pt6355 v1.6 19 symbol min. nom. max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 - 0.20 d 12.00 bsc d1 10.00 bsc e 12.00 bsc e1 10.00 bsc e 0.80 bsc 0 3.5 7 1 0 - - 2 11 12 13 3 11 12 13 l 0.45 0.60 0.75 l1 1.00 ref r1 0.08 - - r2 0.08 - 0.20 s 0.20 - - ccc 0.10 notes: 1. all dimensions are in millimeters. 2. refer to jedec ms-026 bcb.
pt6355 v1.6 20 important notice princeton technology corporation (ptc ) reserves the right to make co rrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product wit hout notice at any time. ptc cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ptc product. no circuit patent licenses are implied. princeton technology corp. 2f, 233-1, baociao road, sindian, taipei 23145, taiwan tel: 886-2-66296288 fax: 886-2-29174598 http://www.princeton.com.tw

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